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RISC-V: Trim language around the CHERI ISA being a design space. #78

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merged 1 commit into from
Aug 1, 2023

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bsdjhb
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@bsdjhb bsdjhb commented Jul 21, 2023

CHERI-RISC-V's definition is more concrete with fewer alternatives than when the specification was first written. The only remaining design space choice is 32-bit vs 64-bit which is probably not enough to justify the remaining language. This does still keep the idea of a design space in the list of goals motivating the initial desire to apply CHERI to RISC-V as that list is largely historical.

CHERI-RISC-V's definition is more concrete with fewer alternatives
than when the specification was first written.  The only remaining
design space choice is 32-bit vs 64-bit which is probably not enough
to justify the remaining language.  This does still keep the idea of a
design space in the list of goals motivating the initial desire to
apply CHERI to RISC-V as that list is largely historical.
@bsdjhb bsdjhb requested review from rwatson, brooksdavis and swm11 July 21, 2023 22:08
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bsdjhb commented Jul 21, 2023

I suspect Robert is unlikely to review this before the end of the month (when we'd like to have V9 ready). I believe this is inline with the pitch we wish to use for V9 though.

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This makes sense to me. There are certainly some open questions around things like compartmentalization mechanisms, final encodings, etc but we've largely made the big decisions around register files, exceptions, etc.

@PeterRugg
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FWIW, when I was reading through, this section doesn't make sense (the list of one item is referred to in the plural) so can't be left as is. I would definitely just remove it.

@bsdjhb bsdjhb merged commit 4f8cf96 into main Aug 1, 2023
@bsdjhb bsdjhb deleted the riscv_rm_design_space branch August 1, 2023 18:39
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3 participants